A Framework for System Level Verification: The SystemC Case

Ali Habibi, Ph.D. Concordia University, 2005 The advancement in the hardware area made it possible the integration of a complete yet complex system on a single chip (called System-on-a-Chip: SoC). Over 10 million gates, integrated together and running a real time optimized software red crossed classical design techniques. The payback of this advancement resides in the challenge facing SoC designers who have to decide which System Level Language (SLL) to use and how the verification task will be accomplished. Among several SLL proposals, SystemC is expected to make a stronger effect in the area of system level architecture, co-design and integration of hardware and software . The SystemC library of classes and simulation kernel extend C++ to enable the modeling of a complete SoC. Classical verification techniques when used with SystemC face several problems related to the object-oriented aspect of this library and to the complexity of its simulation environment. In this thesis, we overview the main proposals in defining an SLL then we present our proposed methodology to verify SoC designs modeled in SystemC. To this end, we introduce a hybrid approach combining static code analysis, model checking and assertion based verification. We also propose to augment the approach by a test iii